Topic
66 posts tagged “Hardware”.
Chisato · · 4 min read The northbridge and southbridge were the two chips that routed data between a CPU, memory, and peripherals before modern SoCs absorbed their jobs.
The Lycoris Team · · 4 min read Write amplification is when a system writes more data physically than the logical write requested, wearing out storage faster and hurting throughput.
Chisato · · 4 min read Virtual memory gives every process its own private address space, mapped to physical RAM by the OS and CPU — enabling isolation, swapping, and overcommit.
Chisato · · 4 min read NVLink and PCIe both move data to and from GPUs, but NVLink trades PCIe's universality for far higher bandwidth between GPUs specifically.
Chisato · · 5 min read Simultaneous multithreading lets one physical CPU core run two instruction streams at once, filling idle execution units to raise throughput.
Chisato · · 4 min read A TLB is a small CPU cache that stores recent virtual-to-physical address translations, avoiding a slow page-table walk on every memory access.
Kurumi · · 5 min read SanDisk's fiscal Q4 2026 revenue jumped 372% to $8.97B with 84.6% gross margin as datacenter NAND booms. Here are the numbers, guidance, and what to watch.
Chisato · · 5 min read Cache coherence keeps each CPU core's private cache consistent with the others. The MESI protocol is the classic mechanism that makes it work.
Chisato · · 5 min read Memory interleaving spreads consecutive addresses across multiple memory banks so the system can access them in parallel instead of one at a time.
Chisato · · 5 min read Endianness decides whether a multi-byte number's most or least significant byte is stored first in memory. Why it matters and how to spot it.
Chisato · · 4 min read Speculative execution lets a CPU guess ahead and run instructions before it knows they're needed, buying speed at the cost of the timing side channels behind Spectre and Meltdown.
Chisato · · 5 min read Confidential computing uses hardware-isolated enclaves to keep data encrypted even while it's being processed, not just at rest or in transit.
Chisato · · 4 min read A systolic array is a grid of processing elements that pass data to their neighbors in rhythm, built to accelerate matrix multiplication in AI chips like TPUs.
Chisato · · 4 min read SIMD lets a CPU apply one instruction to multiple data points at once. How vectorization works, why compilers auto-vectorize loops, and its limits.
Chisato · · 4 min read DMA lets peripherals move data to and from memory without the CPU copying every byte, freeing the processor to do other work during transfers.
Chisato · · 4 min read Branch prediction guesses which way an if-statement will go before the CPU knows, and out-of-order execution reorders instructions to keep pipelines full.
Chisato · · 4 min read Thermal throttling automatically reduces a chip's clock speed when it gets too hot, trading performance for safety. How it works and how to spot it.
Chisato · · 4 min read TDP is the amount of heat a cooling system must dissipate for a chip, not a hard limit on its power draw. Why TDP and actual power draw often diverge.
Chisato · · 4 min read An ASIC is a chip custom-built for one task, trading flexibility for speed and power efficiency. How ASICs differ from GPUs and FPGAs, and when to use one.
Chisato · · 4 min read China has begun limited mass production of home-grown immersion DUV lithography machines, with first units bound for SMIC, Hua Hong and CXMT. What it changes.
Chisato · · 4 min read UEFI is the firmware that initializes hardware and boots the OS on modern computers, replacing BIOS with faster boot times, larger disk support, and Secure Boot.
Kurumi · · 6 min read SK Hynix reports Q2 2026 earnings July 29 with record profit expected on HBM demand — the memory supercycle's first real test this season. What to watch.
Chisato · · 4 min read CXL is an interconnect standard that lets CPUs, GPUs, and memory devices share coherent memory over PCIe, enabling memory pooling and expansion.
Chisato · · 4 min read NUMA gives each CPU its own local memory bank, so access speed depends on which processor is asking. How NUMA nodes and remote access latency work.
Chisato · · 5 min read RAID combines multiple drives into one logical unit for redundancy, speed, or both. How RAID 0, 1, 5, 6, and 10 trade off capacity, speed, and safety.
Chisato · · 4 min read PCIe (PCI Express) is the high-speed serial bus connecting GPUs, SSDs, and network cards to a CPU. How lanes, generations, and bandwidth work.
Chisato · · 4 min read SSDs store data in flash memory chips with no moving parts; HDDs use spinning magnetic platters. How that difference plays out in speed, cost, and durability.
Chisato · · 4 min read Bandwidth measures how much data memory moves per second; latency measures how long one access takes. Why chips need both, not just one.
Chisato · · 7 min read Nvidia detailed its Vera CPU — 88 custom Olympus cores, 1.2 TB/s memory, and SPEC CPU 2026 scores that edge AMD's Epyc dual-socket flagship.
The Lycoris Team · · 4 min read A quantum computer uses qubits in superposition and entanglement to explore many possible states at once, rather than one bit value at a time.
Chisato · · 4 min read ECC memory detects and corrects single-bit errors in RAM automatically, using extra parity bits — critical for servers where silent corruption is costly.
Chisato · · 4 min read DDR and GDDR are both DRAM, but optimized for opposite goals: DDR minimizes latency for CPUs, GDDR maximizes bandwidth for GPUs. Here's how they diverge.
Chisato · · 4 min read A DPU is a specialized chip that offloads networking, storage, and security tasks from the CPU. How data processing units fit alongside CPUs and GPUs.
Chisato · · 4 min read A process node like '5nm' or '3nm' names a chipmaker's manufacturing generation, not a literal measurement anymore. Here's what the number means.
Chisato · · 6 min read Japan and Nvidia launched Noetra, a 140MW Vera Rubin AI factory with 27,500 GPUs, to build sovereign robotics foundation models under the FRONTia plan.
Kurumi · · 5 min read Intel is the first to mass-produce logic chips on ASML's High-NA EUV, dual-qualifying select 18A Panther Lake layers. Here's what shipped and why it matters.
Chisato · · 4 min read A TPM is a dedicated chip that generates and stores cryptographic keys in hardware, isolated from the operating system. Here's what it actually does.
Chisato · · 5 min read RISC and CISC are two philosophies for CPU instruction sets — simple fixed-length instructions versus fewer, complex ones. How they differ and why.
Chisato · · 4 min read A system on chip packs a CPU, GPU, memory controller, and other components onto one die — the design behind phones, laptops, and most modern chips.
Chisato · · 5 min read ARM and x86 are the two dominant CPU instruction set architectures — how RISC vs CISC design differs and why it affects power and performance.
Chisato · · 4 min read EUV lithography uses 13.5nm-wavelength light to etch the finest features on modern chips. How it works and why it's a chokepoint in chip manufacturing.
Chisato · · 4 min read SRAM is fast, expensive, six-transistor memory used for CPU caches; DRAM is slower, cheaper, one-transistor memory used for main system memory.
Chisato · · 5 min read L1, L2, and L3 CPU caches sit between the processor and main memory, trading capacity for speed at each level. How the hierarchy actually works.
Chisato · · 4 min read An FPGA is a chip whose logic circuits can be reconfigured after manufacturing, sitting between fixed-function ASICs and general-purpose CPUs in flexibility.
Chisato · · 5 min read A chiplet is a small, self-contained die that's packaged together with others to form one chip. How chiplets work and why the industry moved to them.
Chisato · · 4 min read Moore's Law is the observation that transistor density on a chip roughly doubles every couple of years. Why it drove decades of gains, and why it's slowing.
Chisato · · 4 min read CPUs excel at sequential logic, GPUs at parallel math, and TPUs at the specific matrix operations behind neural networks. Here's how they compare.
Chisato · · 5 min read Windows on Arm was famous for broken apps. In 2026, most software runs natively and Prism emulation covers the rest. What works, what doesn't, how to check.
Kurumi · · 4 min read Humanoid robots are arriving with $20,000 price tags and rental plans. What a robot worker really costs to build and run — and when it beats a human wage.
Kurumi · · 4 min read AI ambition is measured in gigawatts. What one actually costs to build and power for a year — a back-of-the-envelope teardown of tech's priciest machine.
Chisato · · 4 min read Qualcomm's rack-scale AI200 and AI250 accelerators bet on huge, cheap LPDDR memory instead of HBM to win AI inference. How the design works and who's buying.
Chisato · · 4 min read Qualcomm's second-generation laptop chip jumps to 18 cores, 5 GHz, and an 80 TOPS NPU. What changed from the Snapdragon X Elite — and whether it matters.
Kurumi · · 3 min read Hyperscalers are pouring record sums into AI data centers, chips, and power. What's driving the capex boom, who profits, and the risk if demand stalls.
Chisato · · 4 min read An NPU is a processor built for one job: running AI models fast at very low power. What TOPS numbers actually mean and why every new laptop ships with one.
Kurumi · · 2 min read Micron has whipsawed in 2026 — record highs on AI memory demand, sharp drops on rate fears, AI-capex doubts, and a Google compression breakthrough. What's moving it.
Chisato · · 6 min read Google TurboQuant compresses AI model memory ~6x with no accuracy loss or retraining, and speeds attention up to 8x. How it works and what it means for HBM.
Kurumi · · 3 min read Micron and Anthropic signed a four-pillar agreement — memory co-design, a multi-year supply deal, Claude adoption, and a Series H investment. Here's what it means.
Kurumi · · 6 min read The AI memory supercycle, explained: why HBM demand outran supply, how DRAM pricing turned, what could end the boom, and what it means for chip stocks.
The Lycoris Team · · 3 min read China unveiled a $295 billion, five-year national AI infrastructure plan — one of the largest state AI commitments ever. Here's the scale and the strategic stakes.
Chisato · · 3 min read A GPU packs thousands of small cores built for parallel arithmetic. Originally for graphics, it's now the engine behind training and running AI models.
Chisato · · 3 min read High-Bandwidth Memory stacks DRAM dies vertically beside the processor, delivering far more bandwidth than DDR5 or GDDR — and AI hardware depends on it.
Kurumi · · 2 min read Samsung, SK Hynix, and Micron are racing to mass-produce HBM4 and win NVIDIA's orders. Inside the next phase of the memory supercycle — and who's ahead.
Chisato · · 2 min read AMD's Instinct MI400 brings 432GB of HBM4 and a full-rack Helios system to challenge NVIDIA in 2026. Here's what the MI455X packs and why it matters.
Chisato · · 2 min read OpenAI and NVIDIA unveiled a landmark deal: at least 10 gigawatts of NVIDIA systems and up to $100 billion in investment, starting on the Vera Rubin platform.
Chisato · · 2 min read NVIDIA unveiled Vera Rubin — a platform of six new chips designed to work as a single AI supercomputer — while its Vera CPU enters full production. What's coming.
The Lycoris Team · · 6 min read RISC-V is a free, open instruction set architecture anyone can implement without royalties. How it works, why it matters, and where it's already winning.
