Chisato · · 4 min read Wafer-Scale Integration Explained
Wafer-scale integration builds one giant chip from an entire silicon wafer instead of cutting it into dies. How it works and its tradeoffs.
Topic
43 posts tagged “Chips”.
Chisato · · 4 min read Wafer-scale integration builds one giant chip from an entire silicon wafer instead of cutting it into dies. How it works and its tradeoffs.
The Lycoris Team · · 6 min read Apple's September 9 'Surprise and shine' event is set to unveil the iPhone 18 Pro and a first foldable iPhone — the first launch under new CEO John Ternus.
Kurumi · · 6 min read Gimlet Labs raised $300M at a $3B valuation in a Series B led by a16z to scale its multi-silicon inference cloud for agentic AI. The backers, the tech, the stakes.
Kurumi · · 6 min read Broadcom's fiscal Q3 2026 revenue hit a record $29.6B as AI chip sales more than tripled to $16.7B, but light Q4 guidance sent the stock lower.
Kurumi · · 5 min read Broadcom reports fiscal Q3 on September 2 with AI semiconductor revenue guided to $16 billion. Here's the setup, the numbers, and what to watch.
Kurumi · · 5 min read Andreessen Horowitz raised $1.1 billion for its Machine Age Fund to back chips, data centers, and robotics — the physical buildout behind the AI boom.
Chisato · · 4 min read Yield is the share of chips on a wafer that work. It's the single biggest driver of chip cost, and why new process nodes start out expensive.
Chisato · · 5 min read 2.5D packaging places dies side by side on an interposer; 3D packaging stacks dies vertically through silicon vias. How advanced packaging works.
Chisato · · 4 min read SerDes converts parallel data to a serial stream for transmission and back, letting chips move data over fewer, faster wires with less overhead.
Chisato · · 4 min read Chip fabrication turns a silicon wafer into a working processor through photolithography, etching, doping, and packaging — here's the full process.
Chisato · · 4 min read An ASIC is fixed-function silicon built for one job at massive scale; an FPGA is reconfigurable hardware you can rewire after it ships. How to choose.
Chisato · · 4 min read Silicon photonics moves data with light instead of electrical signals on standard chip manufacturing lines. How it works and why AI data centers need it.
Chisato · · 5 min read Anthropic reportedly signed an initial $250M deal for Fractile's DRAM-less SRAM inference chips, and the UK startup is now raising near a $6.5B valuation.
Chisato · · 4 min read Binning sorts identical die designs by how well each one actually performs after manufacturing, turning natural process variation into a full product lineup.
Chisato · · 4 min read DRAM stores each bit as a charge in a capacitor that needs constant refreshing; SRAM stores each bit in a transistor circuit that holds its state.
Chisato · · 5 min read Nvidia is in early talks with South Korean AI chip startup Rebellions on a partnership, investment, or acquisition. What Rebellions builds and why it matters.
Chisato · · 4 min read A TPU is a chip built specifically for the matrix math behind neural networks, using a systolic array instead of a general-purpose GPU pipeline.
Chisato · · 5 min read Google's Pixel 11 ships with Tensor G6, the first phone chip on TSMC's 2nm process, running Gemini Nano on-device. Specs, price, and what's new.
Kurumi · · 6 min read Cerebras' Q2 2026 cloud revenue jumped 281% on the OpenAI ramp and it raised full-year guidance, yet the stock fell. The numbers, the RPO, and the warrant math.
Chisato · · 4 min read UCIe is an open standard for wiring chiplets from different vendors into one package, defining the physical layer, protocols, and packaging it needs.
Kurumi · · 6 min read Micron closed above $1,000 for the first time as SanDisk, Western Digital and chip-equipment makers rallied on surging HBM and DRAM demand.
Chisato · · 5 min read A memory controller is the circuit that manages every read and write between the CPU and main memory, setting the ceiling on bandwidth and latency.
Kurumi · · 5 min read Nvidia's Q2 13F disclosed a $21B SpaceX stake and a $30B Intel windfall, revealing a $63B equity portfolio tightly tied to its own chip customers.
Chisato · · 6 min read L&T's Vyoma.AI will build India's largest Nvidia B300 AI Factory in Chennai — 10,000 GPUs for Together AI — under a Rs 10,000–15,000 crore order.
Chisato · · 4 min read Von Neumann shares one memory for code and data; Harvard architecture splits them. How the two computer architectures differ, and where each is used.
Kurumi · · 5 min read UK startup OLIX raised $312M at a $3.3B valuation for its optical AI inference chips, backed by Arm and Reed Hastings. What the photonic bet means.
Chisato · · 5 min read The Trump administration is drafting an FCC ban on Chinese optical transceivers for US data centers. Who wins, who loses, and what it means for AI.
Kurumi · · 6 min read Tesla and SpaceX confirmed Terafab, a $16.8B first-phase chip fab in Grimes County, Texas, with plans to reach 1 terawatt of compute a year. The details.
Chisato · · 5 min read Cache coherence keeps each CPU core's private cache consistent with the others. The MESI protocol is the classic mechanism that makes it work.
Chisato · · 4 min read Branch prediction guesses which way an if-statement will go before the CPU knows, and out-of-order execution reorders instructions to keep pipelines full.
Chisato · · 4 min read An ASIC is a chip custom-built for one task, trading flexibility for speed and power efficiency. How ASICs differ from GPUs and FPGAs, and when to use one.
Kurumi · · 6 min read Samsung and SK Hynix signed roughly $950 billion in chip-supply deals with US tech giants including Nvidia at Korea's San Francisco AI summit. The breakdown.
Chisato · · 4 min read Nvidia and SK Group unveiled a $500B+ AI partnership locking in SK Hynix HBM4 supply and a 2GW AI factory in Korea. Here are the details and what to watch.
Chisato · · 4 min read CXL is an interconnect standard that lets CPUs, GPUs, and memory devices share coherent memory over PCIe, enabling memory pooling and expansion.
Chisato · · 7 min read Nvidia detailed its Vera CPU — 88 custom Olympus cores, 1.2 TB/s memory, and SPEC CPU 2026 scores that edge AMD's Epyc dual-socket flagship.
Chisato · · 4 min read A DPU is a specialized chip that offloads networking, storage, and security tasks from the CPU. How data processing units fit alongside CPUs and GPUs.
Chisato · · 4 min read A process node like '5nm' or '3nm' names a chipmaker's manufacturing generation, not a literal measurement anymore. Here's what the number means.
Chisato · · 5 min read RISC and CISC are two philosophies for CPU instruction sets — simple fixed-length instructions versus fewer, complex ones. How they differ and why.
Chisato · · 4 min read A system on chip packs a CPU, GPU, memory controller, and other components onto one die — the design behind phones, laptops, and most modern chips.
Chisato · · 5 min read ARM and x86 are the two dominant CPU instruction set architectures — how RISC vs CISC design differs and why it affects power and performance.
Chisato · · 4 min read An FPGA is a chip whose logic circuits can be reconfigured after manufacturing, sitting between fixed-function ASICs and general-purpose CPUs in flexibility.
Chisato · · 6 min read AI chipmaker SambaNova closed the first tranche of a $1B Series F at an $11B valuation and named JPMorgan Chase as an on-prem inference customer. The details.
Chisato · · 4 min read Moore's Law is the observation that transistor density on a chip roughly doubles every couple of years. Why it drove decades of gains, and why it's slowing.